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LTC1428-50 Micropower 8-Bit Current Sink Output D/A Converter
FEATURES
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DESCRIPTION
The LTC (R)1428-50 is a micropower 8-bit current sink output D/A converter (DAC) with an output range of 0A to 50A. In 3.3V or 5V systems, the DAC IOUT pin can be biased from 2V to 10V. Supply current is only 130A. Shutdown mode drops the supply current to 0.2A. The LTC1428-50 communicates with external circuitry by using one of three interface modes: standard 3-wire serial mode or one of two pulse modes. Upon power-up, the internal counter resets to 10000000B, the DAC output assumes midrange and the chip configures to 3-wire or pulse mode depending on the CS signal level. In 3-wire mode, the system MPU can serially transfer 8-bit data to and from the LTC1428-50. In pulse mode, the upper six bits of the DAC output program for incrementonly (1-wire interface) or increment/decrement (2-wire interface) operation depending on the D IN signal level. In increment-only mode, the counter rolls over and sets the DAC to zero if the counter increases beyond full scale. In increment/decrement mode, the counter stops incrementing at full scale, stops decrementing at zero scale and does not roll over. LTC1428-50 is available in an 8-pin SO package.
, LTC and LT are registered trademarks of Linear Technology Corporation. Triple Mode is a trademark of Linear Technology Corporation.
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Precision Full-Scale DAC Output Current at 25C: 50A 3% Wide Output Voltage DC Compliance: 2V to 10V Wide Supply Range: 3V VCC 6.5V Supply Current in Shutdown: 0.2A Low Supply Current: 130A Available in 8-Pin SO Triple ModeTM Interface 1. Standard 3-Wire Mode 2. 1-Wire Pulse Mode Interface: Increment-Only 3. 2-Wire Pulse Mode Interface: Increment/Decrement DAC Value Read Back Capability in 3-Wire Mode DAC Powers Up at Midrange DAC Contents Are Retained in Shutdown
APPLICATIONS
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LCD Contrast Control Backlight Brightness Control Power Supply Voltage Adjustment Battery Charger Voltage/Current Adjustment GaAs FET Bias Adjustment Trimmer Pot Elimination
TYPICAL APPLICATION
Digitally Controlled LCD Bias Generator (Standard 3-Wire Mode)
L1 D1 VOUT 15.75V TO 27.75V IN STEPS OF 47mV 15mA FROM 2 CELLS 5V 1 R2 22k R3 22k 2 IOUT VCC DOUT DIN 8 7 VCC MPU (e.g., 8051) P1.3 P1.2 P1.1 P1.0
1428-50 TA01
R1 240k VIN SHDN 2 CELLS 1F SHDN SW LT (R)1307 FB GND VC 4700pF 100k L1: 4.7H MURATA-ERIE LQH3C D1: MBR0530 OR 1N4148
C1 0.1F
LTC1428-50 3 4 SHDN CLK GND CS 6 5
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LTC1428-50
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW IOUT 1 VCC 2 SHDN 3 CLK 4 8 DOUT 7 DIN (UP/DN) 6 GND 5 CS
Supply Voltage (VCC) ................................................ 7V Input Voltage (All Inputs)............ - 0.3V to (VCC + 0.3V) Output Voltage IOUT ...................................................... - 0.3V to 10V DOUT ....................................... - 0.3V to (VCC + 0.3V) Short-Circuit Duration (All Outputs) ............... Indefinite Operating Temperature Range .................... 0C to 70C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1428CS8-50 S8 PART MARKING 14285
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 130C/ W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VCC ICC Supply Current DAC Resolution DAC Full-Scale Current DAC Zero-Scale Current DAC Differential Nonlinearity Supply Voltage Rejection Output Voltage Rejection IOUT Bias Voltage = 2.5V CONDITIONS
VCC = 3.3V, TA = 25C, unless otherwise specified.
MIN
q
TYP 130 0.2 8
MAX 6.5 225 10 51.5 52.5 200 0.9
UNITS V A A Bits A A nA LSB LSB LSB LSB A V V
3.0
VSHDN = VDIN = VCS = VCC, VCLK = 0V, DOUT = NC, IOUT = NC Shutdown
q q
q
48.5 47.5
50 50
IOUT Bias Voltage = 2.5V Monotonicity Guaranteed, No Missing Codes VCC = 3V to 6.5V, Full Scale Current, IOUT Bias Voltage = 2.5V VCC = 5V, Full Scale Current, 2V V(IOUT) 3V VCC = 5V, Full Scale Current, 3V V(IOUT) 10V
q q q q q q q q q q q q q q q
1
4 1
1
4 1
Logic Input Current VIH VIL VOH VOL IOZ High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage
0V VIN VCC VCC = 5V VCC = 3.3V VCC = 5V VCC = 3.3V VCC = 5V, IO = 400A VCC = 3.3V, IO = 400A VCC = 5V, IO = 2mA VCC = 3.3V, IO = 1mA
2.0 1.9 0.80 0.45 2.4 2.1 0.4 0.4 5
Three-State Output Leakage VCS = VCC
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V V V V V V A
LTC1428-50
RECO
fCLK tCKS tCSS tDV tDS tDH tDO tCKHI tCKLO tCSH tDZ tCKH tCSLO tCSHI
E DED OPERATI G CO DITIO S
CONDITIONS
SYMBOL PARAMETER Serial Interface Clock Frequency Setup Time, CLK Before CS Setup Time, CS Before CLK CS to DOUT Valid DIN Setup Time Before CLK DIN Hold Time After CLK CLK to DOUT Valid CLK High Time CLK Low Time CLK Before CS CS to DOUT in Hi-Z CS Before CLK CS Low Time CS High Time
See Test Circuits
See Test Circuits
See Test Circuits fCLK = 2MHz (Note 4) VCLK = 0V
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired.
Note 2: Timing for all input signals is measured at 0.8V for a High-to-Low transition and at 2V for a Low-to-High transition. Note 3: Timing specifications are guaranteed by design but not tested. Note 4: This is the minimum time required for valid data transfer.
TYPICAL PERFORMANCE CHARACTERISTICS
DNL vs Code
1.0 0.8 0.6 0.4 VCC = 3.3V V(IOUT) = 2.5V TA = 25C 1.0 0.8 0.6 0.4
INL (LSB)
FULL-SCALE OUTPUT CURRENT (LSB)
INL vs Code
VCC = 3.3V V(IOUT) = 2.5V TA = 25C
2.0 1.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0
DNL (LSB)
0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 - 1.0 0 32 64 96 128 160 192 224 256 CODE
1428-50 G01
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192 224 256 CODE
1428-50 G02
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VCC = 5V, unless otherwise specified. (Notes 2, 3)
MIN
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TYP
MAX 2
UNITS MHz ns ns ns ns ns ns ns ns ns
150 400 150 150 150 150 200 250 150 400 400 4550 400 400
ns ns ns ns ns
Supply Voltage Rejection
V(IOUT) = 2.5V TA = 25C
1
2
3 5 4 SUPPLY VOLTAGE (V)
6
7
1428-50 G03
3
LTC1428-50 TYPICAL PERFORMANCE CHARACTERISTICS
Temperature Variation
52.5
FULL-SCALE OUTPUT CURRENT (LSB)
FULL-SCALE OUTPUT CURRENT (A)
VCC = 3.3V V(IOUT) = 2.5V
-2 -4
ZERO-SCALE CURRENT (nA)
51.5
50.5
49.5
48.5
47.5 - 55
- 25
35 65 95 5 TEMPERATURE (C)
PIN FUNCTIONS
IOUT (Pin 1): DAC Current Sink Output. In 3.3V or 5V systems, the DAC IOUT pin can be biased from 2V to 10V. VCC (Pin 2): Voltage Supply (3V VCC 6.5V). This supply must be kept free from noise and ripple by bypassing directly to a ground plane. SHDN (Pin 3): Shutdown. A logic low puts the chip into shutdown mode. The digital setting for the DAC is retained. CLK (Pin 4): Shift Clock. This clock synchronizes the serial data and has a Schmitt trigger input. CS (Pin 5): Chip Select Input. In 3-wire mode, a logic low enables the LTC1428-50. Upon power-up, a logic high puts the chip into pulse mode. If CS ever goes low, the chip is configured into 3-wire mode until VCC is reset. GND (Pin 6): Ground. Ground should be tied directly to a ground plane. DIN (UP/DN)(Pin 7): Data Input. In 3-wire mode, the DAC data is shifted into DIN. In pulse mode, upon power-up a logic high puts the counter into increment-only mode. If DIN ever goes low, the counter is configured in increment/ decrement mode until VCC is reset. DOUT (Pin 8): Data Output. In 3-wire mode, on every conversion DOUT serially outputs the previous 8-bit DAC data. In pulse mode, DOUT is three-stated.
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125
1428-50 G04
Bias Voltage Rejection
2 0 0.06 ZERO-SCALE OUTPUT CURRENT (LSB) 0.05 0.04 0.03 -6 -8 -10 -12
155
Zero-Scale IOUT vs Temperature
20 18 16 14 12 10 8 6 4 2 0 0 10 40 30 20 50 TEMPERATURE (C) 60 70 V(IOUT) = 5V V(IOUT) = 2.5V V(IOUT) = 10V VCC = 3.3V
0.02 0.01 0 0 2 4 6 8 10 12 IOUT BIAS VOLTAGE (V) 14 16
VCC = 3.3V TA = 25C
1428-50 G05
1428-50 G06
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LTC1428-50
BLOCK DIAGRA
POWER-ON RESET
CLK DIN CS SHDN CONTROL LOGIC
TEST CIRCUITS
Load Circuit for t DO
1.4V 3k DOUT 100pF
1428-50 TC01
Voltage Waveforms for t DO
CLK 0.8V t DO DOUT 2.4V 0.4V
1428-50 TC03
W
LATCH AND LOGIC UP ONLY/ UP/DN VOLTAGE REFERENCE SHDN LATCH AND LOGIC MODE SELECT 0 = PULSE 1 = SPI SHDN 8-BIT CURRENT DAC IOUT 8 CLK 8-BIT REGISTER/COUNTER UP/DN 8 8 CLK 9-BIT SHIFT REGISTER DOUT (LSB) Q9 DOUT
1428-50 BD
Load Circuit for tDZ, t DV
3k DOUT 100pF
5V t DZ WAVEFORM 2, t DV t DZ WAVEFORM 1
1428-50 TC02
Voltage Waveforms for t DZ, tDV
CS 2.0V 0.8V
DOUT WAVEFORM 1 (SEE NOTE 1) DOUT WAVEFORM 2 (SEE NOTE 2)
2.4V t DZ
90%
t DV
0.4V
10%
1428-50 TC04
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY CS NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY CS
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LTC1428-50
SERIAL I/O OPERATI G SEQUE CE
tCSLO CS tCKS CLK tCSS DIN D7 tDV DOUT Hi-Z D7 D6 D5 D4 D3 D6 D5 tDS D4 tDH D3 tDO D2 D1 D0 D2 D1 tCKLO D0 tDZ D7 Hi-Z
1428-50 F01
Figure 1. 3-Wire Interface Timing Specification
APPLICATIONS INFORMATION
8-BIT CURRENT OUTPUT DAC The LTC1428-50 is an 8-bit, current sink output digital-toanalog (DAC) converter. The LTC1428-50 is guaranteed monotonic and is digitally adjustable in 256 equal steps. Upon power up, the counter resets to 1000000B and the DAC output assumes midrange. The IOUT pin can be biased from 2V to 10V. The LTC1428-50 features a full-scale output current of 50A 3% at room temperature (5% over temperature). This device also includes a flexible serial digital interface that allows easy interconnection to a variety of digital systems. DIGITAL INTERFACE Automatic Mode Selection The LTC1428-50 includes a serial interface capable of communicating with the host system using one of three protocols; standard 3-wire mode, a 2-wire up/down pulse mode and a 1-wire increment-only pulse mode. The LTC1428-50 is designed to autoconfigure itself depending on the method
POWER-UP CS GOES LOW 3-WIRE MODE DIN (UP/DN) GOES LOW INCREMENT/ DECREMENT CS STAYS HIGH PULSE MODE DIN STAYS HIGH INCREMENTONLY
1428-50 F02
Figure 2. LTC1428-50 Operating Modes
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tCSHI
tCKHI
tCSH
tCKH
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of data presentation. A diagram illustrating this autodetection behavior is shown in Figure 2. At power-up, the interface is set to 1-wire pulse mode. If the CS line ever goes low (as it will at the beginning of a valid 3-wire serial transfer) the chip immediately reconfigures itself into 3-wire mode and remains in this mode until power is cycled. If CS stays high, the device stays in pulse mode and monitors the UP/DN pin to determine whether to switch to 2-wire mode. If UP/DN ever goes low (as it will the first time a "down" command is given) the chip switches into 2-wire pulse mode and remains in this mode until power is cycled. In a properly configured 1-wire system, CS and UP/DN will always remain high. 2-wire pulse mode systems must provide a single logic low pulse before the first data pulses are sent to prevent the LTC1428-50 from remaining in 1-wire mode if the first several pulses are logic high. Standard 3-Wire Mode (Figure 3) Refer to the Serial Interface Operating Sequence in Figure 1. When operating in 3-wire mode, the LTC1428-50 will interface directly with most standard 3- or 4-wire serial interface systems. The clock (CLK) input synchronizes the data transfer with each input bit captured at the rising edge of CLK and each output data bit shifted through DOUT at the falling edge. Data is shifted into and out of the LTC142850 starting with the MSB bit. A falling edge at CS initiates the data transfer and brings the DOUT pin out of three-state. The serial 8-bit data representing the new DAC setting is shifted into the DIN pin. Simultaneously, the previous DAC setting is shifted out of the DOUT pin. After the new data is
LTC1428-50
APPLICATIONS INFORMATION
shifted in, a rising edge at CS transfers the data from the input shift register into the DAC register. The DAC output assumes the new value and the DOUT pin returns to a highimpedance state. IOUT = (B7 B6 B5 B4 B3 B2 B1 B0)IFULLSCALE/255
IOUT VCC 0.1F SHDN CLK CS DIN DOUT DIN AND DOUT CAN BE TIED TOGETHER FOR HALF-DUPLEX DATA TRANSFER
1428-50 F03
1 2
IOUT VCC
DOUT DIN
8 7
LTC1428-50 3 4 SHDN CLK GND CS 6 5
Figure 3. 3-Wire Mode; Serial Interface (3-Wire Control by CS, CLK and DIN)
1-Wire Interface (Pulse Mode, Figure 4) In 1-wire pulse mode, each rising edge at CLK increments the upper six bits of the DAC register by one count. When incremented beyond 11111100B, the counter rolls over and sets the DAC to the minimum value (00000000B). In this way, a single pulse applied to CLK increases the DAC output by a single 4LSB step and 63 pulses decrease the
IOUT VCC 0.1F SHDN CLK
1 2
IOUT VCC
DOUT DIN
8 7
DOUT
LTC1428-50 3 4 SHDN CLK GND CS 6 5
1428-50 F04
Figure 4. Pulse Mode: Increment Only (1-Wire Control by CLK)
TYPICAL APPLICATION
Pulse Mode: Increment-Only (1-Wire Control by CLK) with Voltage Output
RFB 100k VOUT 6 VDD 7 VCC 2 1 2 VBIAS 3 SHDN CLK 3 4 IOUT VCC DOUT DIN 8 7
LT1006 4
VOUT = (IOUT)(RFB) + VBIAS VDD VOUT + 1V, 2V VBIAS 10V
VEE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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DAC output by one step. The last two LSBs are always zero in pulse mode. IOUT = (B7 B6 B5 B4 B3 B2 0 0)IFULLSCALE/255 To configure the LTC1428-50 in 1-wire pulse mode, tie both the CS and DIN pins to VCC. 2-Wire Interface (Pulse Mode, Figure 5) In 2-wire pulse mode, a logic high at UP/DN programs the DAC register to increment and each rising edge at CLK increments the upper six bits of the register by one count. Similarly, a logic low at UP/DN programs the DAC register to decrement and a rising edge at CLK decrements the upper six bits of the register by one count. Each count in 2-wire mode changes the DAC output by a single 4LSB step. The DAC register stops incrementing at 11111100B and stops decrementing at 00000000B and will not roll over in 2-wire pulse mode. The last two LSBs are always zero in pulse mode. IOUT = (B7 B6 B5 B4 B3 B2 0 0)IFULLSCALE/255 To configure the LTC1428-50 in 2-wire pulse mode, tie CS to VCC and bring the UP/DN pin low at least once during power-up.
1 2 8 7
IOUT VCC 0.1F SHDN CLK UP/DN
IOUT VCC
DOUT DIN
DOUT
LTC1428-50 3 4 SHDN CLK GND CS 6 5
1428-50 F05
Figure 5. Pulse Mode; Increment/Decrement (2-Wire Control by CLK and UP/DN)
DOUT
LTC1428-50 SHDN CLK GND CS 6 5
1428-50 TA02
7
LTC1428-50
TYPICAL APPLICATION
Digitally Adjustable 3A Lithium-Ion Battery Charger
R7 500 GND SW D1 MBR340 L1** 10H D2 1N4148 200pF SPIN OVP SENSE RS3 200 1% 0.47F BOOST LT1511 COMP1 CLP CLN VCC C1 1F DIN RS4 ADAPTER CURRENT SENSE VIN (ADAPTER INPUT) 11V TO 25V TO MAIN SYSTEM POWER R5 UNDERVOLTAGE LOCKOUT R6 5k
NOTE: COMPLETE LITHIUM-ION CHARGER, NO TERMINATION REQUIRED. RS4, R7 AND C1 ARE OPTIONAL FOR IIN LIMITING *TOKIN 25V CERAMIC SURFACE MOUNT **10H COILTRONICS CTX10-4 CONSULT LT1511 DATA SHEET FOR R5 VALUE
PACKAGE DESCRIPTIO
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP
0.016 - 0.050 0.406 - 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER LTC1329 LTC1451 LTC1452 LTC8043 DESCRIPTION 8-Bit Current Output D/A Converter 12-Bit Micropower Serial Input VOUT DAC 12-Bit Multiplying Serial Input VOUT DAC 12-Bit Multiplying Serial Input IOUT DAC COMMENTS Current Source Output, Full-Scale Current 10A or 50A Higher Resolution, 8-Pin SO Higher Resolution, 8-Pin SO Higher Resolution, 8-Pin SO
1428f LT/TP 0198 4K * PRINTED IN USA
8
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417 q (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com
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10F
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CIN* 10F
UV PROG VC BAT RS2 200 1% 1k 0.33F 300 CPROG 1F RPROG 4.93k 1%
RS1 0.033 BATTERY CURRENT SENSE
R3 332k 1% BATTERY VOLTAGE SENSE R4 162k 1%
+
COUT 22F TANT
+ +
1 3.3V 2
VBAT 7.5V VBAT 24V IN STEPS OF 65mV
IOUT VCC
DOUT DIN
8 7 MPU (e.g., 8051) P1.2 P1.1 P1.0
50pF
LTC1428-50 3 4 SHDN CLK GND CS 6 5
1428-50 TA03
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 0.053 - 0.069 (1.346 - 1.752) 0.004 - 0.010 (0.101 - 0.254) 8 7 6 5
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
SO8 0996
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(c) LINEAR TECHNOLOGY CORPORATION 1998

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